RTL Design Engineer
Markham, ONAMD, Inc.
Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.
Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools
ASIC Design Engineer, PCIe IP Enablement
Markham, ONAMD, Inc.
Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, synthesis and CDC tool experience, and knowledge of low-power design are expected.
Verilog, UPF, CPF
Silicon Design Engineer (1 year contract)
Markham, ONAMD, Inc.
Candidates need a bachelor's or master's in computer or electrical engineering. Preferred experience includes scripting in Perl, Python or Shell, C++, SQL, VLSI knowledge and AI/ML applications.
Perl, Python, TCL, C++, SQL
Summer 2027 Long Term Hardware Design Engineering Intern/Co-Op
Markham, ONAMD, Inc.
Candidates need to be enrolled in a Canadian university bachelor's program in electrical or computer engineering or a related field. Knowledge of semiconductor devices, digital logic, VLSI, Verilog or VHDL, scripting, and Linux/Unix is strongly encouraged.
Verilog, VHDL, Perl, TCL, Linux, UNIX
Summer 2027 Long Term Hardware Design Engineering Intern/Co-Op
Vancouver, BCAMD, Inc.
Candidates need to be enrolled in a Canada based university bachelor's program in electrical or computer engineering or a related field. Knowledge of Verilog or VHDL, ASIC design, physical design and Linux/Unix is an asset, and valid work authorization is required.
Verilog, VHDL, Perl, TCL, UNIX, Linux
Short Term 2027 Data Analyst Intern/Co-Op
Markham, ONAMD, Inc.
Candidates need to be enrolled in a Canadian university undergraduate program in a data or engineering field. Experience with Python, SQL, R, Java, data processing, cloud services and visualization tools is strongly encouraged.
Power BI, Snowflake, Oracle, SQL Server, Microsoft Azure, Kubernetes
Short Term 2027 Hardware Design Engineering Intern/Co-Op
Markham, ONAMD, Inc.
Candidates need to be enrolled in a Canadian university bachelor's program in electrical or computer engineering or a related field. Knowledge of Verilog or VHDL, digital logic, VLSI, ASIC design and scripting or Linux environments is an asset. Valid work authorization is required.
Verilog, VHDL, Perl, TCL, Ruby, C
SoC DFX Scan / ATPG Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
Lead Diagnostics Software Engineer, ATE Integration
Markham, ONAMD, Inc.
8+ ansAMD, Inc. asks for 8+ years of silicon engineering experience in validation, diagnostics or test, strong C/C++ and Python skills, and hands-on ATE experience. Candidates also need knowledge of structural pattern generation and GFX or compute architectures, and a bachelor's, master's or PhD in an engineering or computer science field.
V93000, UltraFLEX, GitHub, CI/CD pipelines, C/C++, Python
SoC DFX Scan / ATPG Engineer
Ottawa, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
Silicon Design Engineer - Technical Lead
Markham, ONAMD, Inc.
AMD needs candidates with experience in I/O protocols such as USB, PCIe and CXL, plus micro-architecture and RTL design for multi-clock, high-frequency, low-power designs. A master's or bachelor's in electrical engineering or equivalent is preferred.
Python, Perl
RTL Design Engineer
Markham, ONAMD, Inc.
Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. A bachelor's or master's degree in electrical engineering or equivalent is preferred.
Python, Perl
SoC Lead Engineer – LEC & Low Power Signoff
Markham, ONAMD, Inc.
Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.
Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler