DFT Engineer, Senior
Toronto, ONQualcomm Canada ULC
2+ ansCandidates need a bachelor's degree in an engineering or computer science field with 2+ years of hardware engineering experience, or a master's with 1+ year. They need hands-on DFT, ATPG, and test-pattern experience plus scripting skills.
Python, Tcl, Perl
DFT Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL
DFT Engineer (Senior to Staff level)
Toronto, ONQualcomm Canada ULC
10+ ansCandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL
FY27 Intern - Digital Design Engineering Intern - Canada (16 months)
Toronto, ONQualcomm Canada ULC
Candidates need to be working toward a bachelor's degree in engineering, computer science or a related field, with strong digital design fundamentals. Verilog or VHDL knowledge and scripting in Perl, Python or TCL are required, with DFT concepts, Tessent, C/C++ or SystemVerilog as assets.
Verilog, VHDL, Perl, Python, TCL, Siemens Tessent
FY27 Intern - Qualcomm SoC Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
1+ ansQualcomm Canada ULC needs students pursuing a Bachelor's or Master's in electrical or computer engineering, computer science or AI/ML, available May or June 2027 to August or September 2028. Candidates need strong programming skills in C, C++ or Python and digital logic fundamentals.
Verilog, SystemVerilog, EDA tools
Staff Engineer, Physical Design/Implementation
Toronto, ONQualcomm Canada ULC
3+ ansCandidates need a Master's degree with 3+ years or a Bachelor's with 4+ years of ASIC physical design experience. They need hands-on skill with industry chip design tools and strong knowledge of timing, power and clocking.
Cadence Innovus, Synopsys ICC2
Engineer
Markham, ONQualcomm Canada ULC
1+ ansCandidates need a bachelor's degree in engineering or a related field, plus 6 months to 2 years of experience in chip design, VLSI or digital design, including internships. They should understand digital logic and timing, know basic physical design steps, and have scripting skills in Python, Tcl, Perl or Shell.
Verilog, SystemVerilog, EDA tools