SoC DFX Scan / ATPG Engineer
Ottawa, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
SoC Design Lead, Microarchitecture and Design Methodology
Markham, ONAMD, Inc.
Candidates need a strong foundation in computer architecture and digital design, along with static timing analysis, clock and power optimization knowledge. Experience with Verilog or SystemVerilog, and UVM preferred, plus strong communication and teamwork skills.
Verilog, SystemVerilog, UVM
SoC Lead Engineer – LEC & Low Power Signoff
Markham, ONAMD, Inc.
Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.
Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler