Design Verification Engineer — Memory Subsystem (Vancouver)
Vancouver, BCSur place
Qualcomm Canada ULC
3+ ansCandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.
Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers
Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels)
Markham, ONSur place
Qualcomm Canada ULC
4+ ansCandidates need an engineering degree and, for senior roles, several years of ASIC design or verification experience. Strong skills in UVM, SystemVerilog, digital logic and scripting in Python or CShell are expected, along with good problem solving and communication.
SystemVerilog, UVM, Python, CShell