ASIC Digital Design, Architect
Markham, ONS
Synopsys
10+ ansCandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.
Verilog, VHDL, synthesis tools, DFT tools
Principal Physical Design Methodology Engineer
Markham, ONS
Synopsys
10+ ansCandidates need a Bachelor's or Master's in Electrical or Computer Engineering and 10+ years of ASIC digital implementation experience. Deep expertise with Fusion Compiler or ICC2, high-speed IP experience, and Tcl and Python scripting are required.
Fusion Compiler, ICC2, Innovus, PrimeTime, PrimePower, Tcl