Emulation Performance/Debug Engineer
Markham, ONQualcomm Technologies, Inc.
2+ ansCandidates need a bachelor's degree in science or engineering with 2+ years of ASIC work, or a master's with 1+ year. Experience with emulation platforms, Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure is preferred.
Veloce, Palladium, Xilinx FPGA, Intel FPGA, JTAG, Python
SoC Debug Engineer, Senior Staff
Markham, ONQualcomm Technologies, Inc.
9+ ansCandidates need 9+ years of pre-silicon and post-silicon bring-up and debug experience, RTL understanding, and hands-on use of JTAG and lab equipment such as logic analyzers and oscilloscopes. A Master's in Computer or Electrical Engineering is required, along with the stated years of ASIC design or validation experience.
JTAG, Logic analyzer, Signal generator
SoC Debug Engineer, Staff
Markham, ONQualcomm Technologies, Inc.
6+ ansCandidates need 6+ years of pre-silicon and post-silicon bring-up and failure analysis experience, plus RTL understanding and JTAG and lab equipment skills. A Master's in Computer or Electrical Engineering is required, along with ASIC experience.
JTAG, Logic analyzer, Signal generator