ASIC/RTL Design Engineer 5 # 26-27793
Markham, ONContrat
UT
US Tech Solutions
Candidates need strong ASIC synthesis and static timing analysis experience with EDA tools such as Design Compiler and PrimeTime. Experience with UPF/CPF, RTL coding in Verilog or SystemVerilog, and scripting in TCL, Perl, Python or Shell is expected.
Synopsys Design Compiler, PrimeTime, PrimePower, Power Artist