Emplois “tcl” au Canada – Page 7

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• 1 mois

  FPGA Designer

  Sainte-Anne-de-Bellevue, QC

  Temps plein

  

  MDA

  5+ ansCandidates need a bachelor's degree in electrical engineering or equivalent and five years of FPGA or ASIC design experience. They need VHDL skills, tool knowledge (Synplify, Questa, Vivado, Libero), Linux scripting, and bilingual English and French communication.

  Synplify, Modelsim, Questa, Vivado, Libero, Jira

• 1 mois

  Junior Hardware Engineering Developer, FPGA

  Ottawa, ON

  HybrideTemps plein

  

  General Dynamics Missions System International

  Candidates need a bachelor's degree in electrical or computer engineering (recent graduates welcome), hands-on FPGA project experience, and basic VHDL or Verilog skills. They must be eligible to work in Canada and able to obtain a Canadian government security clearance.

  Xilinx Vivado, Git, oscilloscope, logic analyser, FPGA prototyping board

• 1 mois

  Senior Mining Engineer

  Vancouver, BC

  Sur placeTemps plein

  

  RE/SPEC Inc.

  10+ ansCandidates need a mining, geological or civil engineering degree and at least 10 years in mining engineering, including 2 years in operations. They must be a registered professional engineer, a Qualified Person under SEC S-K 1300 or NI 43-101, and skilled in mine planning software.

  Surpac, Vulcan, MineSched, Deswik, Carlson, GIS

• 1 mois

  Network Engineer in Solution Test

  Vancouver, BC

  Sur placeTemps plein

  

  Arista Networks

  3+ ansCandidates need a master's degree in a related field, 3+ years of system or solution test experience on complex networks, and detailed knowledge of layer 2 and layer 3 networking. Strong communication skills and some scripting in Python or TCL are also required.

  Linux ping, traceroute, tcpdump, iperf, strace, industry-standard CLI and SNMP interfaces, traffic generators

• 1 mois

  System Validation Engineer

  Markham, ON

  Sur placeTemps plein

  

  NETINT Technologies Inc.: NETINT Technologies develops custom silicon for ultra-high-density video encoding and processing in the data center.

  Candidates need an MS or BS in electrical or computer engineering, and experience in system validation or ASIC/FPGA design. They need embedded firmware skills in C/C++ and scripting skills in Python, TCL or Perl, plus knowledge of ARM CPU and GPU architectures.

  Lab equipment, Debugger tools, Prototype boards, Python, TCL, Perl

• 1 mois

  Experience IT Systems Administrator

  Ottawa, ON

  Sur placeTemps plein

  A

  Arcadion

  1+ ansCandidates need an undergraduate degree or technologist diploma from a Canadian-accredited program, plus one to two years of relevant experience. Strong networking knowledge (routing, switching, Juniper), virtualization, Microsoft 365/Azure and troubleshooting skills are needed.

  Juniper, Fortinet, Aruba, VMware, Hyper-V, KVM

• 1 mois

  Director of Construction

  Kelowna, BC

  Sur placeTemps plein

  

  Troika Management Corp: Troika Developments is a progressive, future-focused land and real estate development company based in Kelowna, BC.

  15+ ans8+ gestionTroika Management Corp needs a candidate with 15+ years of construction leadership, including 8 years managing Project Managers and experience running over $250M in concurrent projects. A construction-related degree or equivalent experience is required, with knowledge of the BC Building Code.

  Civil engineering, Construction management, PMP, P.Eng., Red Seal, LEED

• 1 mois

  Static Timing Analysis (STA) Engineer

  Toronto, ON

  Temps plein

  A

  Altera

  6+ ansCandidates need 6+ years of static timing analysis experience on ASIC or FPGA designs, plus a strong grasp of STA fundamentals and tools such as PrimeTime. A bachelor's or master's degree in electrical or computer engineering, with RTL design knowledge, is required.

  PrimeTime, Verilog, SystemVerilog, Tcl, Python

  1 mois

  FPGA Compiler (Placer) Engineer

  Toronto, ON

  Temps plein

  A

  Altera

  6+ ansCandidates need 6+ years in FPGA or ASIC CAD, EDA tools or physical design, strong algorithms skills, and C/C++ experience. A bachelor's or master's in electrical, computer engineering or computer science is required.

  Quartus, Vivado, C++, Python, Tcl

• 1 mois

  Engineer, Digital Design Verification

  Ottawa, ON

  Temps plein

  S

  Semtech_Canada_Corporation

  2+ ansCandidates need a B.Sc. in Electrical or Computer Engineering and at least 2 years of industry experience. Semtech Canada Corporation expects knowledge of UVM-style verification, SystemVerilog, scripting in Python, TCL, Perl or C, and Linux.

  SystemVerilog, UVM, Python, TCL, Perl, Linux

  1 mois

  Senior Design/Verification Engineer

  Burlington, ON +1

  Temps plein

  S

  Semtech_Canada_Corporation

  5+ ansCandidates need a B.Sc. in Electrical or Computer Engineering and 5+ years of industry experience, with expert knowledge of constrained random verification (UVM, OVM, AVM or VMM) and SystemVerilog. Scripting skills in Python, TCL, Perl or C and working knowledge of Linux are also required.

  SystemVerilog, UVM, Python, TCL, Perl, Linux

  1 mois

  Analog Design Intern

  Ottawa, ON

  Temps plein

  S

  Semtech_Canada_Corporation

  Candidates need a good grasp of analog electronics and the ability to learn quickly. Experience with transistor-level design, CAD tools like Cadence Virtuoso, and Python or Matlab scripting would be assets.

  Cadence Virtuoso, Python, Matlab, Skill, TCL

  1 mois

  Principal NPI Test Engineer

  Burlington, ON

  Temps plein

  S

  Semtech_Canada_Corporation

  12+ ansCandidates need a bachelor's degree in an engineering field, 12+ years in semiconductor test including 8+ years in mixed-signal or RF test, and a proven record leading NPI programs for high-speed communication ICs.

  Advantest V93000, SmarTest 7/8, Cadence, Altium

• 1 mois

  Senior Formal Verification Engineer - LPU

  Télétravail au Canada

  TélétravailTemps plein

  NC

  NVIDIA Canada Dev. Inc.

  12+ ansCandidates need a BS, MS or PhD in computer science, computer engineering or electrical engineering, 12+ years of ASIC verification with 8+ years in formal methods, mastery of SystemVerilog Assertions, experience with a major formal tool such as JasperGold or VC Formal, and scripting skills in Tcl or Python.

  VC Formal, SystemVerilog, Tcl, Python

• 1 mois

  Electrical Engineer/FPGA Designer

  Ottawa, ON

  Temps plein

  LO

  Lumentum Ottawa ULC

  3+ ansCandidates need a Bachelor's or Master's in electrical, computer or a related engineering field, and 3+ years of FPGA design and verification in VHDL, Verilog or SystemVerilog. Hands-on experience with high-speed digital design, hardware debugging and FPGA tools is also expected.

  Xcelium, Xilinx Vivado, Altera Quartus, oscilloscope, logic analyzer, spectrum analyzer

  1 mois

  Senior FPGA Design/Verification Engineer

  Ottawa, ON

  Temps plein

  LO

  Lumentum Ottawa ULC

  Candidates need strong experience designing and simulating FPGA or ASIC logic in Verilog or SystemVerilog, plus synthesis, timing and clock domain crossing skills. Strong debugging, communication and attention to detail are also required.

  Verilog, SystemVerilog, Altera FPGA tools

  1 mois

  FPGA Designer

  Ottawa, ON

  Temps plein

  LO

  Lumentum Ottawa ULC

  Candidates need experience designing ASIC or FPGA logic in Verilog or SystemVerilog, including synthesis, timing and clock domain crossing, plus AMD (Xilinx) or Altera tools. Strong debugging skills and clear communication are required.

  Xilinx, Altera, Verilog, SystemVerilog

• 1 mois

  Principal DSP Firmware Engineer

  Ottawa, ON

  107k–157k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  6+ ansCandidates need an MSc or PhD in electrical or computer engineering or a related field, plus at least 6 years of DSP or embedded software experience. Strong C/C++, Python, TCL and RTOS skills are required, along with good debugging and communication skills.

  C/C++, Python, TCL, Jira, Git, Confluence

  1 mois

  Principal Engineer - Design

  Burnaby, BC

  86k–186k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  10+ ansMicrochip Semiconductor Canada ULC needs candidates with a BS or MS in electrical or computer engineering and 10+ years of experience. Strong skills in serial protocols, Linux, C, Python and HDL design are required.

  Cadence Palladium, Cadence Protium, FPGA, protocol analyzers, test and defect tracking tools

  1 mois

  Principal Engineer -Design

  Saskatoon, SK

  Temps plein

  MS

  MCHP Semiconductor Canada ULC

  10+ ansCandidates need 10 years of experience in synthesis, static timing analysis and formal verification, plus tapeout experience on 16nm or smaller processes. Strong scripting skills and a degree in computer science or electrical/VLSI engineering are required.

  Cadence Genus, TCL, Perl, Python, UPF, CPF

  1 mois

  Sr Engineer I - Validation (Systems)

  Burnaby, BC

  86k–186k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  5+ ansCandidates need at least 5 years of silicon or SoC validation experience, strong C/C++ and Python (or Tcl) skills, and hands-on lab work with high-speed test equipment. A bachelor's or master's degree in computer or electrical engineering or computer science is required.

  Oscilloscopes, Protocol analyzers, Logic analyzers, FPGAs, Validation boards, Lab equipment

  1 mois

  Principal Engineer - Validation (Systems)

  Burnaby, BC

  86k–186k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  10+ ansCandidates need 10 years of silicon or SoC validation experience, strong C/C++ and Python skills, and hands-on lab experience with high-speed test equipment. A Bachelor's or Master's in electrical or computer engineering or computer science is required.

  Oscilloscope, Protocol analyzer, Logic analyzer, FPGA, Emulation platform, Validation board

  1 mois

  Technical Staff Engineer - Design

  Burnaby, BC

  107k–226k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  12+ ansCandidates need a B.S. in electrical engineering with 12+ years of related experience, hands-on pad ring and bump map work for advanced SoC designs, and knowledge of IO standards such as SerDes, DDR, PCIe and CXL. Scripting skills in Tcl or Python are required.

  Orbit IO, ISP, Tcl, Python, Verilog, SVN

• 1 mois

  Principal Engineer - Analog Design

  Ottawa, ON

  107k–157k $/anTemps plein

  MC

  Microchip - Canada

  5+ ansCandidates need a Master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal circuit experience. Microchip Technology prefers experience with ADCs, DACs, filters, PLLs, DLLs and high-speed I/Os, plus scripting in SKILL, Python, Perl or Tcl.

  Cadence, Verilog-A, SKILL, Python, Perl, Tcl

13 entreprises