Emplois “Verilog” au Canada – Page 9

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• 1 mois

  ASIC Development Engineer

  Burnaby, BC

  76k–114k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  2+ ansCandidates need a Bachelor's in Electrical or Computer Engineering and 2+ years of relevant industry experience, or a Master's in the same field. They need strong C++ or Python scripting, debugging and problem-solving skills, and clear written and verbal communication.

  Verilog, VHDL, C++, Python

  1 mois

  Senior SoC Design Engineer

  Burnaby, BC

  86k–186k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  3+ ansCandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.

  Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl

  1 mois

  Senior Engineer - Analog Design

  Ottawa, ON

  Temps plein

  MS

  MCHP Semiconductor Canada ULC

  3+ ansCandidates need a Master's or PhD in Electrical Engineering and about 3 to 5 years of analog or mixed-signal IC design experience. They should know PLLs, ADCs, filters or high-speed I/O and use Cadence IC design tools.

  Cadence IC design tools, Verilog-A, Skill, Python, Perl, Tcl

  1 mois

  Senior Technical Staff Engineer - Analog Design

  Ottawa, ON

  Temps plein

  MS

  MCHP Semiconductor Canada ULC

  10+ ansCandidates need a Master's or Doctorate in Electrical Engineering or a related field and 10+ years of analog and mixed-signal IC design experience, including PLLs, DLLs, ADCs, DACs and high-speed I/O. Strong skills in Cadence tools, scripting and multi-site teamwork are required.

  Cadence, Verilog-A, Skill, Python, Perl, Tcl

  1 mois

  Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design

  Montréal, QC

  Temps plein

  MS

  MCHP Semiconductor Canada ULC

  10+ ansMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse

  Cadence IC, Verilog-A, Skill, Python, Perl, Tcl

  1 mois

  Senior Engineer II - Physical Design

  Burnaby, BC

  86k–186k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  7+ ansCandidates need a 4-year Electrical or Electronics Engineering degree and 7.5+ years of ASIC development experience. They need hands-on skill in synthesis, static timing and place and route for high-performance designs, plus Python, Perl or TCL scripting.

  Verilog, VHDL, Python, Perl, TCL

  1 mois

  Senior Manager-Design Engineering

  Burnaby, BC +2

  Temps plein

  MS

  MCHP Semiconductor Canada ULC

  12+ ansCandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience and proven experience leading engineering teams. Strong coaching skills, debugging ability and Verilog or VHDL design experience are required; SOC, communication protocols, Synopsys or Cadence tools and 28nm process experience are assets.

  Verilog, VHDL, Synopsys, Cadence

• 1 mois

  Principal Engineer - Analog Design

  Toronto, ON +1

  107k–157k $/anTemps plein

  MC

  Microchip - Canada

  5+ ansCandidates need a Master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal circuit experience. Microchip Technology prefers experience with ADCs, DACs, filters, PLLs, DLLs and high-speed I/Os, plus scripting in SKILL, Python, Perl or Tcl.

  Cadence, Verilog-A, SKILL, Python, Perl, Tcl

  1 mois

  Ingénieur principal en analogique/ Principal Engineer - Analog Design

  Montréal, QC

  Temps plein

  MC

  Microchip - Canada

  5+ ansCandidates need a master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal design experience. Strong skills in high-speed circuits, Cadence IC tools, scripting and Verilog-A are expected.

  Cadence IC, Verilog-A, Skill, Python, Perl, Tcl

• 1 mois

  Senior ASIC Design Engineer - Client IP

  Ottawa, ON

  112k–179k $/anTemps plein

  CC

  Ciena Canada ULC

  5+ ansCandidates need an engineering degree at the bachelor or master level and 5+ years of SystemVerilog design and digital synthesis, timing closure and clock-crossing experience. Strong independent problem solving, English communication, and knowledge of verification and timing/power/area trade-offs are required.

  Git, Jira, Python, Make, bash

  1 mois

  Senior ASIC Verification Engineer, onsite Kanata

  Ottawa, ON

  109k–174k $/anTemps plein

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs candidates with an engineering or science degree at the BEng/BSc or MEng/MSc level and familiarity with formal verification. Candidates should know standards such as OTN, B100G and Ethernet, and programming in Python, C, C++ or SystemC.

  Python, C, C++, Make, bash

• 1 mois

  Senior NPU Architect

  Télétravail au Canada

  Télétravail

  

  EnCharge AI

  5+ ansCandidates need a BS or MS in EE, CS or a related field with 5-8 years of relevant experience, or a PhD with 2-4 years. Knowledge of computer architecture, digital design, AI/ML workloads, C/C++, Python and Verilog or SystemVerilog is required.

  C++ simulation framework, Verilog, Python

• 1 mois

  Optical DSP Design Engineer

  Ottawa, ON

  CC

  Celero Communications, Inc.

  2+ ansCandidates need a strong background in digital signal processing, digital communications and fiber-optic systems, plus a Master's or PhD in electrical engineering, physics or mathematics. Two or more years of industry experience and programming in C/C++, Python or MATLAB are preferred.

  MATLAB, Python, C++, Verilog, VHDL, GitHub

  1 mois

  DSP - FEC Design Engineer

  Ottawa, ON

  CC

  Celero Communications, Inc.

  Candidates need a strong background in coding theory, digital communications and error correction, plus experience with forward error correction for communication systems. A master's or PhD in a related field and programming skills in C/C++, Python or MATLAB are preferred.

  MATLAB, Python, C++, GitHub, Verilog, VHDL

• 1 mois

  Power Architect

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  15+ ansCandidates need 15+ years of experience with power estimation tools, deep knowledge of power-gating, voltage domains and leakage control, and a record of reducing design power through architectural changes. Proficiency in Verilog, Design Compiler, C/C++ and Python is required.

  PowerArtist, PtPX, RTL Architect, PrimePower, Verilog HDL, Design Compiler

• 1 mois

  CPU Micro-Architect / RTL (Lead & IC Engineers)

  Canada

  HybrideTemps plein

  

  NUVACORE

  7+ ansCandidates need a BS or MS with 15+ years of CPU design experience for leads or 7+ years for individual contributors. They must know Verilog, simulation and logic and physical design, and understand RISC-V, ARM64 or x86 ISAs.

  Verilog, AI tools for RTL coding, simulation tools, emulation

• 1 mois

  Senior Embedded Software Designer

  Toronto, ON

  HybrideTemps plein

  

  Kepler Communications

  6+ ansCandidates need 6+ years of embedded software experience on high-reliability systems, strong C/C++ skills, and embedded Linux or RTOS experience. A bachelor's degree or equivalent practical experience is required.

  Git, Yocto, FreeRTOS

• 1 mois

  Senior FPGA Designer

  Montréal, QC

  HybrideTemps plein

  E

  Exegy

  5+ ansDiplôme en génie électronique, électrique ou informatique; Cinq ans ou plus d'expérience en conception FPGA; Maîtrise avancée du VHDL et/ou du Verilog

  Vivado, Git, Jenkins, Python, Linux

• 1 mois

  Senior Digital Design Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ ansCandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.

  SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl

• 1 mois

  Concepteur – Électronique Analogique & Digitale / Designer – Analog & Digital Electronics (future opportunities)

  Montréal, QC

  Sur place

  

  Syntronic

  5+ ansBaccalauréat en génie électrique ou électronique; 5 ans d'expérience en conception et validation de circuits; Maîtrise d'OrCAD/Allegro, Altium ou Xpedition

  OrCAD, Allegro, Altium, Xpedition, Matlab, SPICE

• 1 mois

  Analog/Mixed Signal Architect

  Toronto, ON

  

  Lightmatter

  Candidates need a PhD in electrical engineering, physics, applied physics or a related analog discipline, plus experience designing optical receivers and transmitters in advanced CMOS. Strong simulation skills in Cadence Virtuoso and Spectre, clear written communication and problem-solving on open-ended problems are also required.

  Cadence Virtuoso, Cadence Spectre, Verilog-A, IBIS-AMI

• 1 mois

  FPGA Engineer

  Toronto, ON

  HybrideTemps plein

  

  Cerebras Systems

  5+ ansCerebras Systems needs candidates with 5+ years of production FPGA experience (or a Master's/PhD plus 3 years), Verilog skill in a Git repository, and strong FPGA place-and-route, timing closure and debug skills. Knowledge of TCP, RoCE and Wireshark, plus network switch familiarity, is also required.

  Verilog, Git, Wireshark, Arista, Juniper

• 1 mois

  Senior ASIC (Front End) Design Engineer

  Toronto, ON

  Hybride

  

  Ethernovia, Inc.

  10+ ansCandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.

  Verilog, Perl, TCL, C/C++, Make

  1 mois

  Senior ASIC Design Verification Engineer

  Télétravail au Canada

  Télétravail

  

  Ethernovia, Inc.

  10+ ansCandidates need a BS or MS in electrical engineering, computer science or a related field, and at least 10 years of ASIC verification experience. Required skills include SystemVerilog, UVM, Python, TCL and C/C++, plus strong debugging and communication abilities.

  Verilog, UVM, Python, TCL, C/C++, SystemC

14 entreprises