Emulation Performance/Debug Engineer
Markham, ONSur place
QT
Qualcomm Technologies, Inc.
2+ ansCandidates need a bachelor's degree in science or engineering with 2+ years of ASIC work, or a master's with 1+ year. Experience with emulation platforms, Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure is preferred.
Veloce, Palladium, Xilinx FPGA, Intel FPGA, JTAG, Python
Senior Emulation Performance Methodology & Debug Engineer
Markham, ONSur place
QT
Qualcomm Technologies, Inc.
4+ ansCandidates need a bachelor's, master's or PhD in a science or engineering field with 4+, 3+ or 2+ years of ASIC design or verification experience respectively. Preferred: 5+ years in emulation and silicon environments, plus Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure skills.
Veloce, Palladium, FPGA prototyping, JTAG debugger, Xilinx FPGA, Intel FPGA