Programmeur FPGA (intermédiaire)
Montréal, QCTemps plein
GS
Groupe SII
Candidates need hands-on FPGA design experience in VHDL and/or Verilog, UVM verification and simulation tools such as ModelSim or Questasim. They also need knowledge of DO-254 processes, Git and the ability to work on-site in Montréal at least 3 days per week.
Questasim, ModelSim, Aldec Active-HDL, Git