Senior FPGA Design/Verification Engineer
Ottawa, ONTemps plein
LO
Lumentum Ottawa ULC
Candidates need strong experience designing and simulating FPGA or ASIC logic in Verilog or SystemVerilog, plus synthesis, timing and clock domain crossing skills. Strong debugging, communication and attention to detail are also required.
Verilog, SystemVerilog, Altera FPGA tools
FPGA Designer
Ottawa, ONTemps plein
LO
Lumentum Ottawa ULC
Candidates need experience designing ASIC or FPGA logic in Verilog or SystemVerilog, including synthesis, timing and clock domain crossing, plus AMD (Xilinx) or Altera tools. Strong debugging skills and clear communication are required.
Xilinx, Altera, Verilog, SystemVerilog