Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)
Markham, ONSur place
Qualcomm Canada ULC
2+ ansCandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.
SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools
Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels)
Markham, ONSur place
Qualcomm Canada ULC
4+ ansCandidates need an engineering degree and, for senior roles, several years of ASIC design or verification experience. Strong skills in UVM, SystemVerilog, digital logic and scripting in Python or CShell are expected, along with good problem solving and communication.
SystemVerilog, UVM, Python, CShell