FPGA Digital Design Engineer (6+ month Contract)
Toronto, ONTélétravailTemps plein, Contrat
Kepler Communications
5+ ansCandidates need a bachelor's degree in computer or electrical engineering, 5+ years of FPGA/RTL design experience, and skill in Verilog, SystemVerilog or VHDL. They also need Xilinx Zynq or UltraScale experience, timing and clock domain crossing knowledge, and scripting skills.
Vivado, Quartus, ModelSim, Python, Tcl