Formal Verification Engineer
Markham, ONHybrideTemps plein
NUVACORE
4+ ansCandidates need a degree in electrical or computer engineering, computer science or mathematics, or equivalent experience. They must have hands-on formal verification experience, strong SystemVerilog and assertion skills, CPU microarchitecture knowledge and Python scripting.
SystemVerilog, Verilog, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python