Program Manager – High-Speed SerDes IP
Toronto, ONTalentlab
8+ ansCandidates need 8+ years in the semiconductor industry with a focus on high-speed SerDes IP, a Bachelor's in Electrical Engineering or a related field, and a solid understanding of IP deliverables and integration. PMP certification and ASIC or protocol knowledge are assets.
Jira, MS Office
Senior Design Verification Engineer
Toronto, ONTalentlab
3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Staff Physical Design Engineer
Toronto, ONTalentlab
5+ ansCandidates need 5+ years of physical design experience on digital ASICs, including advanced nodes like TSMC N5, N4P or N3. They must know industry EDA tools, PnR, timing analysis and physical verification, and be strong in TCL, Python or Perl.
Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, TCL
Staff ASIC Design Engineer – AI/ML Hardware IP
Toronto, ONTalentlab
5+ ansCandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.
Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass