Senior Design Verification Engineer
Toronto, ONTalentlab
3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Staff ASIC Design Engineer – AI/ML Hardware IP
Toronto, ONTalentlab
5+ ansCandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.
Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass
Senior Staff ASIC Design Egineer - AI/ML Hardware IP
Toronto, ONTalentlab
6+ ansCandidates need six or more years of ASIC design and integration experience (or a Master's plus five years, or a PhD plus four), strong Verilog/SystemVerilog skills, and experience owning complex SoC blocks. A Bachelor's, Master's or PhD in electrical engineering or a related field is required, and the candidate must be legally authorized to work in Canada.
Verilog, SystemVerilog, VCS, Verdi, Questa, Xcelium