Mask Layout Designer
Markham, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's degree in an electrical or computer field with 4+ years of custom layout experience, or equivalent experience. They also need 4+ years using layout and verification tools such as Cadence, LVS and rmap.
Cadence, LVS, rmap
Cross-Functional Engineer, Staff
Toronto, ON +1Qualcomm Canada ULC
4+ ansCandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
Staff Engineer, Physical Design/Implementation
Toronto, ONQualcomm Canada ULC
3+ ansCandidates need a Master's degree with 3+ years or a Bachelor's with 4+ years of ASIC physical design experience. They need hands-on skill with industry chip design tools and strong knowledge of timing, power and clocking.
Cadence Innovus, Synopsys ICC2
SOC Design Engineer
Markham, ON +2Qualcomm Canada ULC
4+ ansCandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.
Spyglass, Design Compiler, Cadence LEC, Perl, TCL