FY27 Intern - Digital Design Engineering Intern - Canada (16 months)
Toronto, ONQualcomm Canada ULC
Candidates need to be working toward a bachelor's degree in engineering, computer science or a related field, with strong digital design fundamentals. Verilog or VHDL knowledge and scripting in Perl, Python or TCL are required, with DFT concepts, Tessent, C/C++ or SystemVerilog as assets.
Verilog, VHDL, Perl, Python, TCL, Siemens Tessent
FY27 Intern - Qualcomm SoC Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
1+ ansQualcomm Canada ULC needs students pursuing a Bachelor's or Master's in electrical or computer engineering, computer science or AI/ML, available May or June 2027 to August or September 2028. Candidates need strong programming skills in C, C++ or Python and digital logic fundamentals.
Verilog, SystemVerilog, EDA tools
FY27 Intern - Digital Design Engineering Internship - Canada (16 months)
Toronto, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's program in electrical or computer engineering, computer science or a related field, with graduation in November 2028 or later. Experience with Verilog or SystemVerilog, RTL design and at least one year of programming in C, C++ or Python is required, with FPGA or tapeout experience as a plus.
Verilog, SystemVerilog, FPGA, EDA tools
FY27 Intern - Soft IP ASIC Engineering Internship - Canada (12 or 16 months)
Ottawa, ONQualcomm Canada ULC
1+ ansQualcomm Canada needs candidates studying toward a bachelor's degree in electrical, computer or engineering science, or computer science. They need scripting experience in Python, Perl, TCL or Unix/Linux shell, plus source control experience with SVN, CVS or RCS.
Verilog, SystemVerilog, UVM, SVN, CVS, RCS
DSP Systems Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ ansCandidates need a Bachelor's in engineering or a related field with 4+ years of systems engineering experience, or a Master's with 3+ years, or a PhD with 2+ years. Strong MATLAB, Python and C/C++ skills, plus DSP architecture experience in mixed-signal SerDes, are required.
MATLAB, Python, C/C++, RTL simulation tools
Senior Director, Technology
Ottawa, ONQualcomm Canada ULC
10+ ansCandidates need a bachelor's in electrical engineering with 10 years of ASIC or IP development experience, or a master's with 8 years. They also need hands-on knowledge of Ethernet, UALink and OTN, HDL languages, SystemVerilog UVM and verification methods.
SystemVerilog, Verilog, VHDL, UVM, Unix/Linux, SVN
FY27 Intern - Softip Engineering Co-Op - Canada (4 months)
Ottawa, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's or master's program in electrical, computer or related engineering, with scripting experience in Python, Perl, TCL or Unix/Linux shell and experience with source code revision systems.
Verilog, SystemVerilog, UVM, VHDL, SVN, CVS
DFT Engineer, Senior
Toronto, ONQualcomm Canada ULC
2+ ansCandidates need a bachelor's degree in an engineering or computer science field with 2+ years of hardware engineering experience, or a master's with 1+ year. They need hands-on DFT, ATPG, and test-pattern experience plus scripting skills.
Python, Tcl, Perl
Engineer
Markham, ONQualcomm Canada ULC
1+ ansCandidates need a bachelor's degree in engineering or a related field, plus 6 months to 2 years of experience in chip design, VLSI or digital design, including internships. They should understand digital logic and timing, know basic physical design steps, and have scripting skills in Python, Tcl, Perl or Shell.
Verilog, SystemVerilog, EDA tools
FY27 Intern - Edge AI and Display Hardware Architecture Development Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
Qualcomm Canada ULC needs candidates enrolled in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028 and graduating November 2028 or later. Strong analytical skills, programming in C/C++ or Python, and HW modeling and simulation experience are required.
Verilog, VHDL, C/C++, Python, HW simulation tools, HW CAD tools
FY27 Intern - Camera Design Engineering Internship - Canada (12 or 16 months)
Vancouver, BCQualcomm Canada ULC
1+ ansCandidates need to be enrolled toward a bachelor's degree in electrical, computer or a related engineering or science field. They need experience in Tcl, Perl, Python and SystemVerilog, plus academic or project VLSI experience as an asset.
Verilog, Tcl, Perl, Python, EDA tools
FY27 Intern - Camera Design Implementation Intern - Canada (16 months)
Vancouver, BCQualcomm Canada ULC
Candidates need to be enrolled in a bachelor's degree in engineering, computer science or a related field, with an expected graduation of November 2028 or later. Strong scripting skills and knowledge of ASIC design flow are needed.
synthesis tools, static timing analysis tools, formal verification tools