Principal Analog IC Designer
Toronto, ON +1Cadence
5+ ansCandidates need at least 5 years of CMOS SerDes or high-speed I/O IC development, a thorough understanding of jitter and signal equalization, and an MS or PhD in electrical engineering. Strong problem-solving, communication and teamwork skills are also required.
Cadence tools
Principal Analog IC Designer
Toronto, ON +1Cadence
5+ ansCandidates need at least 5 years of CMOS SerDes or high-speed I/O experience, a strong grasp of jitter and signal equalization, and proficiency with circuit simulation CAD tools. An MS or PhD in EE is required.
Cadence
IC design Implementation and SignOff Architect, (STA SignOff)
CanadaCadence
15+ ansCandidates need 15+ years of IC design implementation and signoff experience, deep advanced-node STA and ECO skills, and strong scripting in Tcl, Python or Perl. A BS or MS in electrical or computer engineering is required.
Tempus, Certus, QRC
Analog/Mixed-Signal IC Design Co-Op/Intern (Summer 2026) / Stage/Co-Op en Conception de CI Analogiques/Signal Mixte (Été 2026)
Mount Royal, SKCadence
Citoyen canadien ou résident permanent; Inscrit en programme de maîtrise ou de baccalauréat en génie électrique; Excellentes compétences en résolution de problèmes et aptitude en analogique
Problem solving, Communication skills, Work in teams, Electrical engineering