ASIC Design Engineer, PCIe IP Enablement
Markham, ONTemps plein
AI
AMD, Inc.
Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, synthesis and CDC tool experience, and knowledge of low-power design are expected.
Verilog, UPF, CPF
Sr. Staff Physical Design Engineer
Vancouver, BCTemps plein
AI
AMD, Inc.
Candidates need strong experience in high-performance physical design, timing closure and physical signoff, plus proficiency in Python and TCL for flow automation. Experience leading engineers and an electronics or electrical engineering background are preferred.
Synopsys ICC2, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedHawk